20 research outputs found
Event-based Backpropagation for Analog Neuromorphic Hardware
Neuromorphic computing aims to incorporate lessons from studying biological
nervous systems in the design of computer architectures. While existing
approaches have successfully implemented aspects of those computational
principles, such as sparse spike-based computation, event-based scalable
learning has remained an elusive goal in large-scale systems. However, only
then the potential energy-efficiency advantages of neuromorphic systems
relative to other hardware architectures can be realized during learning. We
present our progress implementing the EventProp algorithm using the example of
the BrainScaleS-2 analog neuromorphic hardware. Previous gradient-based
approaches to learning used "surrogate gradients" and dense sampling of
observables or were limited by assumptions on the underlying dynamics and loss
functions. In contrast, our approach only needs spike time observations from
the system while being able to incorporate other system observables, such as
membrane voltage measurements, in a principled way. This leads to a
one-order-of-magnitude improvement in the information efficiency of the
gradient estimate, which would directly translate to corresponding energy
efficiency improvements in an optimized hardware implementation. We present the
theoretical framework for estimating gradients and results verifying the
correctness of the estimation, as well as results on a low-dimensional
classification task using the BrainScaleS-2 system. Building on this work has
the potential to enable scalable gradient estimation in large-scale
neuromorphic hardware as a continuous measurement of the system state would be
prohibitive and energy-inefficient in such instances. It also suggests the
feasibility of a full on-device implementation of the algorithm that would
enable scalable, energy-efficient, event-based learning in large-scale analog
neuromorphic hardware
Gradient-based methods for spiking physical systems
Recent efforts have fostered significant progress towards deep learning in
spiking networks, both theoretical and in silico. Here, we discuss several
different approaches, including a tentative comparison of the results on
BrainScaleS-2, and hint towards future such comparative studies.Comment: 2 page abstract, submitted to and accepted by the NNPC (International
conference on neuromorphic, natural and physical computing
Demonstrating Advantages of Neuromorphic Computation: A Pilot Study
Neuromorphic devices represent an attempt to mimic aspects of the brain's
architecture and dynamics with the aim of replicating its hallmark functional
capabilities in terms of computational power, robust learning and energy
efficiency. We employ a single-chip prototype of the BrainScaleS 2 neuromorphic
system to implement a proof-of-concept demonstration of reward-modulated
spike-timing-dependent plasticity in a spiking network that learns to play the
Pong video game by smooth pursuit. This system combines an electronic
mixed-signal substrate for emulating neuron and synapse dynamics with an
embedded digital processor for on-chip learning, which in this work also serves
to simulate the virtual environment and learning agent. The analog emulation of
neuronal membrane dynamics enables a 1000-fold acceleration with respect to
biological real-time, with the entire chip operating on a power budget of 57mW.
Compared to an equivalent simulation using state-of-the-art software, the
on-chip emulation is at least one order of magnitude faster and three orders of
magnitude more energy-efficient. We demonstrate how on-chip learning can
mitigate the effects of fixed-pattern noise, which is unavoidable in analog
substrates, while making use of temporal variability for action exploration.
Learning compensates imperfections of the physical substrate, as manifested in
neuronal parameter variability, by adapting synaptic weights to match
respective excitability of individual neurons.Comment: Added measurements with noise in NEST simulation, add notice about
journal publication. Frontiers in Neuromorphic Engineering (2019
Emulating insect brains for neuromorphic navigation
Bees display the remarkable ability to return home in a straight line after
meandering excursions to their environment. Neurobiological imaging studies
have revealed that this capability emerges from a path integration mechanism
implemented within the insect's brain. In the present work, we emulate this
neural network on the neuromorphic mixed-signal processor BrainScaleS-2 to
guide bees, virtually embodied on a digital co-processor, back to their home
location after randomly exploring their environment. To realize the underlying
neural integrators, we introduce single-neuron spike-based short-term memory
cells with axo-axonic synapses. All entities, including environment, sensory
organs, brain, actuators, and the virtual body, run autonomously on a single
BrainScaleS-2 microchip. The functioning network is fine-tuned for better
precision and reliability through an evolution strategy. As BrainScaleS-2
emulates neural processes 1000 times faster than biology, 4800 consecutive bee
journeys distributed over 320 generations occur within only half an hour on a
single neuromorphic core
The BrainScaleS-2 Neuromorphic Platform — A Report on the Integration and Operation of an Open Science Hardware Platform within EBRAINS
This report presents the challenges encountered and the solutions created for the operation of the BrainScaleS neuromorphic platform, and the overall progress leading to this state at the end of the Human Brain Project (HBP)
A Scalable Approach to Modeling on Accelerated Neuromorphic Hardware.
Neuromorphic systems open up opportunities to enlarge the explorative space for computational research. However, it is often challenging to unite efficiency and usability. This work presents the software aspects of this endeavor for the BrainScaleS-2 system, a hybrid accelerated neuromorphic hardware architecture based on physical modeling. We introduce key aspects of the BrainScaleS-2 Operating System: experiment workflow, API layering, software design, and platform operation. We present use cases to discuss and derive requirements for the software and showcase the implementation. The focus lies on novel system and software features such as multi-compartmental neurons, fast re-configuration for hardware-in-the-loop training, applications for the embedded processors, the non-spiking operation mode, interactive platform access, and sustainable hardware/software co-development. Finally, we discuss further developments in terms of hardware scale-up, system usability, and efficiency